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mt9d115: 1/5-inch soc digital image sensor features mt9d115 ds rev. e pub. 4/15 en 1 ?semiconductor components industries, llc,2015 1/5-inch system-on-a-chip (soc) cmos digital image sensor mt9d115 datasheet, rev. e for the latest datasheet, please visit www.onsemi.com features ? 2 mp resolution (1600h x 1200v) ? 1/5-inch optical format ? same or better image qu ality compared to mt9d112 ? individual module id su pport through one-time programmable (otp) memory ? surface fit lens correction (lc) to compensate for lens/small pixel vignetting and corner color variations ? automatic functions: exposure, white balance, black level offset correction, flicker detection and avoidance, color saturation control, defect identification and correcti on, aperture correction, and gpio ? programmable controls: exposure, white balance, horizontal and vertical bl anking, color, sharpness, gamma, lens shading correction, horizontal and vertical image flip, zoom, windowing, sampling rates, and gpio ? 15 frames per second (fps) at 1600h x 1200v with moderate pixel clock frequency ( ? 64 mhz) to minimize baseband reception interference and 30 fps at 800h x 600v ? 2 x 2 pixel binning to impr ove low-light image quality ? support for external led or xenon flash ? on-chip phase-locked loop (pll) to minimize the number of system clocks ? low power modes to prolong battery life of portable devices ? fail-safe i/os with programmable output slew rate ? industry standard two-wire serial interface for controls ? 10-bit parallel or mipi serial interfaces for image data applications ? cellular phones ?pc cameras ?pdas notes: 1. power consumption for typical voltages at 800 x 600 video mode table 1: key performance parameters parameter value pixel size 1.75 ? m x 1.75 ? m optical format 1/5-inch array format (active) 1600h x 1200v = 1.92 mp imaging area 2.8 mm x 2.10 mm: 3.50 mm diagonal (4:3 aspect ratio) cra 25 color filter array rgb bayer scan mode progressive shutter electronic rolling shutter (ers) input clock range 6 C 54 mhz output pixel clock maximum 85 mhz output mipi data rate maximum 512 mb/s max. frame rate 15 fps full res 30 fps 800 x 600 responsivity 0.65 v/lux-sec (550 nm) signal-to-noise ratio 39 db (max) dynamic range 63.9 db (pixel) supply voltage digital 1.8 v (nominal) analog 2.8 v (nominal) i/o 1.8 v or 2.8 v (nominal) mipi 1.7-1.95v power consumption 196mw 1 operating temperature range C30c to 70c (at junction) package bare die, csp
mt9d115 ds rev. e pub. 4/15 en 2 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9D115D00STCK25AC1-200 2 mp 1/5" soc die sales, 200 ? m thickness mt9d115eb3stc-cr 2 mp 1/5" cis soc chip tray without protective film mt9d115w00stck25ac1-750 2 mp 1/5" soc wafer sales, 750 ? m thickness
mt9d115 ds rev. e pub. 4/15 en 3 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 decoupling capacitor recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 camera functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 optics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 gpio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 appendix a- v dd _io current addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
mt9d115 ds rev. e pub. 4/15 en 4 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor list of figures list of figures figure 1: mt9d115 block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: soc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: firmware architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: external host register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 6: two-wire serial control bus timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: imaging a scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: six pixels in normal and column mirror readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 11: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 12: eight pixels in normal and column skip 2x readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 13: pixel readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: pixel readout (x_odd_inc = 3, y_odd_inc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: pixel readout (x_odd_inc = 1, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 16: pixel readout (x_odd_inc = 3, y_odd_inc = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 17: pixel readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 18: pixel readout (x_odd_inc = 3, y_odd _inc = 3, x_ybin = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 19: valid image data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 20: pixel data timing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 21: available test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: ifp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: gamma correction curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 24: timing of full frame data or scaled data passing th rough the fifo . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 figure 25: sequencer finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 26: cra vs. image height. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 27: power application sequence timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 28: internal power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 29: hard reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 30: soft reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 31: recommended power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 32: hard standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 33: soft standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 34: output interface timing waveform s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 35: recommended system and test setup for minimum v dd _io power consumption . . . . . . . . . . . . .59 figure 36: reset_bar pad architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 37: recommended system and test setup for minimum v dd _io power consumption in the mt9d115 sharing with multiple two-wire serial interface devices62 figure 38: recommended system and test setup for minimum v dd _io power consumption in the mt9d115 sharing with multiple two-wire serial interface devices at different io levels63 figure 39: system setup with independent voltage sources fo r mt9d115 and controller chip . . . . . . . . . . . .64 figure 40: modifications to the demo2 sensor head board for v dd _io current measurement. . . . . . . . . . . . .65
mt9d115 ds rev. e pub. 4/15 en 5 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: signal description and direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: list of drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: two-wire serial interfac e timing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 6: row address sequencing (sampling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7: row address sequencing (binning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 8: data formats supported by mipi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9: ycbcr output data ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 10: rgb ordering in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 11: 2-byte rgb format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 12: power application sequence timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 13: por parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 14: hard reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 15: soft reset signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 16: power down signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 17: hard standby signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 18: soft standby signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 19: status of signals during different states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 20: gpio related registers and variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 21: maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 22: i/o parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 23: mipi high-speed transmitter dc ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 24: mipi high-speed transmitter ac ch aracteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 25: mipi low-power transmitter dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 26: mipi low-power transmitter ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 27: ac electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 28: dc electricals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 29: status of signals during standby state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 30: typical mismatch current in v dd _io due to mismatch in reset_bar level and v dd _io level . .61
mt9d115: 1/5-inch soc digital image sensor functional description mt9d115 ds rev. e pub. 4/15 en 6 ?semiconductor components industries, llc,2015. functional description the on semiconductor mt9d115 is a 1/5-inch 2 mp cmos digital image sensor with an integrated advanced camera system. this camera system features a microcontroller (mcu), a sophisticated image flow processor (i fp), mipi and parallel output ports (only one output port can be used at a time). th e microcontroller manage s all functions of the camera system and sets key operation parame ters for the sensor core to optimize the quality of raw image data entering the ifp. the ifp will be responsible for processing and enhancing the image. the entire system-on-a-chip (soc) has superior low-light performance that is particu- larly suitable for pc camera applications . the mt9d115 features on semiconductor?s breakthrough low-noise cmos imaging technology that achieves near-ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of cmos. the on semiconductor mt9d115 can be operated in its default mode or programmed for frame size, exposure, gain, and other pa rameters. the default mode output is a 800x600 image size at 30 frames per second (fps), assuming a 24 mhz input clock. it outputs 8-bit data, using the parallel output port. architecture overview the mt9d115 combines a 2 mp sensor core with an ifp to form a stand-alone solution for both image acquisition and processing. both the sensor core and the ifp have internal registers that can be controlled by the user. in normal operation, an integrated microcontroller autonomo usly controls most aspects of operation. the processed image data is transmitted to the host system eith er through the parallel or mipi interface. figure 1 shows the major functional blocks of the mt9d115. figure 1: mt9d115 block diagram pixel array sensor core fifo image flow processor (if p ) stats engine color pipeline parallel output interface microcontroller sram rom por two- wire serial if internal register bus system control m icrocontroller u nit (mcu) mipi formatter
mt9d115 ds rev. e pub. 4/15 en 7 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor typical connections typical connections figure 2: typical configuration (connection) notes: 1. this typical configuration shows only one scenar io out of multiple possibl e variations for this sen- sor. 2. if a mipi interface is not required, the following pads must be left floating: d out _p, d out _n, clk_p, and clk_n. 3. the gpio pads can serve multiple features that can be reconfigured. the function and direction will vary by applications. 4. only one output mode (serial or parallel) can be used at any time. 5. on semiconductor recommends a resistor value of 1.5k ?? to v dd _io for the two-wire serial inter- face r pull - up ; higher values can be used for slower transmission speed. 6. v aa and v aa _pix can be tied together. although separate decoupling capacitors are recommended for v aa and v aa _pix, decoupling capacitors can be shared if one would like to reduce module size. 7. v pp is the otp memory programming voltage and shou ld be left floating during normal operation. 8. 1.8v supply is shared by mipi interface and v dd to reduce the number of decoupling caps, and, sub- sequently, the module size. v dd io_tx must be connected to a 1.8v power supply source, even though mipi interface is not used. 9. on semiconductor recommends that 0.1 ? f and 1 ? f decoupling capacitors for each power supply are mounted as close as possib le to the pad and that a 10 ? f capacitor be placed nearby off-module. actual values and results can vary depending on layout and design considerations. please follow on semiconductor's recommended capacitor recommendations. 10. v dd _pll and v aa can share the same power source, in which case gnd_pll must be connected to gnd. 11. internal pull-up in reset_bar pin and can be left floating when not connected. analog power s data sclk frame_valid pixclk line_valid standby gnd_io a gnd i/o power digital core power v dd pll power v dd _pll v aa 6 v aa _pix 6 slave two-wire serial interface to parallel camera port or 4 r pull-up 5 reset_bar vpp 7 general purpose i/os (flash, oe_bar, d out _lsb[1:0]) gpi0[3:0] 3 s addr standby mode extclk external clock in (6C54 mhz) active low reset d gnd d out [7:0] clk_p d out _p clk_n to serial camera port 2 d out _n v dd io_tx/v dd v aa _pix/v dd _pll/v aa v dd io_tx 8 mipi power tx v dd _io gnd_pll v dd _io 0.1 f 0.1 f 0.1 f
mt9d115: 1/5-inch soc digital image sensor decoupling capacitor recommendations mt9d115 ds rev. e pub. 4/15 en 8 ?semiconductor components industries, llc,2015. decoupling capacitor recommendations it is important to provide clean, well-regulated power to each power supply. the customer is ultimately responsible for ensuring that clean power is provided for their own designs because hardware design is influenced by many factors, including layout, operating conditions, and component selection. the recommendations for capacitor placement and values listed below are based on the on semiconductor internal demo camera design and verified in hardware. on semiconductor recommends the following, in order of preference: 1. mount 0.1 ? f and 1 ? f decoupling capacitors for each power supply as close as possi- ble to the pad and place a 10 ? f capacitor nearby off-module. 2. if module limitations allow for only six decoupling capacitors for a three-regulator design (v dd 1v2 tied to external regulator), use a 0.1 ? f and 1 ? f capacitor for each of the three regulated supplies. on semiconductor also recommends placing a 10 ? f capacitor for each supply off-module, but close to each supply. 3. if module limitations allow for only three decoupling capacitors, use a 1f capacitor (preferred) or a 0.1f capacitor for each of the three regulated supplies. on semicon- ductor also recommends placing a 10f ca pacitor for each supply off-module but close to each supply. 4. give priority to the v aa supply for additional decoupling capacitors. on semiconductor does not recommend inductive filtering components. follow best practices when performing phys ical layout. refer to technical note tn-09- 131.
mt9d115 ds rev. e pub. 4/15 en 9 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor signal descriptions signal descriptions notes: 1. in serial only mode, d out [7:0], pixclk, and gpio[3:0] can be left floating by setting r0x0026[1] =1. if gpio signals are required, d out [7:0] and pixclk must be tied to d gnd and oe_bar must be tied to v dd _io. gpio_3 should be configured as an inpu t for oe_bar function and set r0x001a[8] = 1. 2. gpio can be left floating if not us ed and must be programmed as outputs. 3. must be connected to v dd _io, internal 100k ohms typical at 2.8v vddio used. 4. can be left floating if not used. 5. must be connected to v dd , even in designs where the mipi interface is not used. table 3: signal description and direction name type description note standby input hardware standby extclk input external clock input s addr input two-wire interface device select address sclk input two-wire interface serial clock reset_bar input hardware reset 4 clk_n output mipi differential clock n 5 clk_p output mipi differential clock p 5 d out _n output mipi differential data n 5 d out _p output mipi differential data p 5 d out [7:0] output parallel image data 1 frame_valid output parallel pixel bus frame valid 1 line_valid output parallel pixel bus line valid 1 pixclk output parallel pixel bus pixel clock 1 s data bidirectional two-wire interface serial data gpio_0/d out _lsb[0] bidirectional/output general-purpose i/o or lsb for raw 10 data output during soc bypass 2 gpio_1/d out _lsb[1] bidirectional/output general-purpose i/o or lsb for raw 10 data output during soc bypass 2 gpio_3/oe_bar bidirectional/output gene ral-purpose i/o or output enable 2 gpio_2/flash bidirectional/output general-purpose i/o or flash control 2 v aa supply analog core power source 2.8v nominal v aa _pix supply analog core power source 2.8v nominal v dd supply digital core power source 1.8v nominal v dd _io supply digital io power source 1.8v or 2.8v nominal v dd _pll supply digital pll power source 2.8v nominal v dd io_tx supply digital mipi io po wer source 1.8v nominal. 6
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 10 ?semiconductor components industries, llc,2015. architecture the mt9d115 from on semiconductor is the third-generation, two-megapixel camera soc. it is a microprocessor-based camera sy stem that combines a sensor core with an image flow processor (ifp) to form a standa lone solution that in cludes image acquisi- tion and processing. both the sensor core and ifp have internal registers that can be accessed by an external host. in normal operation, the integrat ed system micropro- cessor autonomously controls most aspects of operation. th e image data is transmitted to the external host system either through a parallel bus or a serial mipi interface (see figure 3). figure 3: soc block diagram sensor core input to ifp interface ifp output from ifp interface register bus master math coprocessor sleep unit mcu gpio 1kb patch ram two-wire serial i/f slave dma 24kb code rom 1kb data ram always on to external host parallel serial peripheral bus (sfr) instruction bus memory data bus register bus (icb)
mt9d115 ds rev. e pub. 4/15 en 11 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture the external host and the integrated microprocessor (mcu) can both access all the internal resources (ram and registers). the ex ternal host always has higher priority. the following sections briefly describe the functionality of each key component of the system. firmware the firmware implements all automatic camera functions, such as auto exposure (ae), auto white balance (awb), and flicker detectio n/avoidance (fd), as we ll as control func- tions such as sequencer, mode/context, and histogram (see table 4). the firmware consists of drivers, generally one driver for each major automatic or control function (see figure 4). figure 4: firmware architecture table 4: list of drivers id driver name description id = 1 sequencer controls of camera main function id = 2 ae auto exposure id = 3 awb auto white balance id = 4 flicker detection flicker detection and avoidance id = 7 mode/context context variables id = 11 histogram reduce image flare and analyze image histogram monitor sequencer operation driver auto function driver hardware auto exposure auto white balance flicker avoidance mode control ram stat ifp core output
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 12 ?semiconductor components industries, llc,2015. external host interface (two-wire slave-only interface) the mt9d115 will appear as a two-wire serial interface slave to the external host. its base address is selectable by the external s addr pin input (when s addr = 0 then base address = 0x78; when s addr = 1 then base address = 0x7a). there are 32k addressable 16- bit registers (that is, the starting address of ea ch register always falls into even addresses) within the mt9d115 but not all of them are being used (see figure 5). figure 5: external host register map the mt9d115 register reference provides detailed register explanations. although most registers are self-explanatory, the next para graphs contain enhanced information about xdma registers are worth explaining here. the xdma registers allow the external host to indirectly access the internal memory resources of the mt9d115, which include the firmware driver variables. to access the variables, use logical accesses provided by the xdma registers. soc2 regs sysctl regs core regs xdma regs 0x0000 0x098c 0x1070 gp io regs 0x3012 soc1 regs 0x3210 0x3400 16-bit driver variables user -loadable memory 1k b 1k b 0x0000 internal memory resource rx_ss regs 0x0102
mt9d115 ds rev. e pub. 4/15 en 13 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture the external host interface is implemented through a two-wire in terface that enables direct read/write access to hardware register s and indirect access to firmware variables within the mt9d115. the interfac e is designed to be compatible with the mipi alliance standard for camera serial interface 2 (csi-2 ) 1.0, which uses the electrical characteris- tics and transfer protocols of the two- wire serial interf ace specifications. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the sensor acts as a slave device to the external host which acts as a master device. the master generates a clock (s clk) that is an input to the sensor and used to synchronize the transactions at the interface. data is transferred between the master and th e slave on a bidirectio nal serial data bus (s data ). both sclk and s data are pulled up to v dd _io off-chip by a 1.5k ? resistor. either the slave or master device can drive s data to low?the interface determines which device is allowed to drive s data at any given time. figure 6: two-wire serial control bus timing s clk s data s clk s data write start ack read start ack t shar t ahsr t sdhr t sdsr read sequence write sequence read address bit 7 read address bit 0 register value bit 7 register value bit 0 write address bit 7 write address bit 0 register value bit 7 register value bit 0 t srts t sclk t sdh t sds t shaw t ahsw stop t stps t stph t srth ack
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 14 ?semiconductor components industries, llc,2015. note: t r and t f are dependent on system-level parameters such as the value of pu ll-up resistor used, how the two-wire serial bus is routed, whether th ere are other devices on the serial bus, and the strength of the supply used to pull-up the serial bus. always-on power domain the always-on power domain (aopd) provides an area of functionalit y that will always be active while power is applied to the mt9d 115. the external host interface is located in the aopd. the domain also includes miscellaneous clock and reset controls as well as configuration registers for the sensor core, processor core, clock configuration, and clock reset control. the user-loadable patch memory is also included in this domain. this memory will remain powered when the main core power is shut down using the standby command. sensor core the sensor core of the mt9d115 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate, qualified by line_valid (lv) and frame_valid (fv). the maximum pixel rate is 30 mp/s, corresponding to a pixel clock rate of 63.25 mhz. see figure 7 on page 15 for a block diagram of the sensor core. it includes a 2.0mp active-pixel array. the timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. in the time interval between reset- ting a row and reading that row, the pixels in the row integrate incident light. the expo- sure is controlled by varying the time interv al between reset and readout. after a row is read, data from the columns are sequenced thro ugh an analog signal chain that provides offset correction and gain, and then through an adc. the output from the adc is a 10-bit value for each pixel in the array. table 5: two-wire serial interface timing data f extclk = 14 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; v dd _phy = na; tj = 70c; c load = 68.5pf symbol parameter conditions min typ max unit f sclk serial interface input clock frequency 100 C 400 khz t sclk serial interface input clock period 2.5 C 10 ? s sclk duty cycle 33 50 50 % t rsclk/s data rise time C C 300 ns t srts start setup time master write to slave 600 C C ns t srth start hold time master write to slave 300 C C ns t sdh s data hold master write to slave 5 C 900 ns t sds s data setup master write to slave 100 C C ns t shaw s data hold to ack master write to slave 150 C C ns t ahsw ack hold to s data master write to slave 150 C C ns t stps stop setup time master write to slave 300 C C ns t stph stop hold time master write to slave 600 C C ns t shar s data hold to ack master read from slave 300 C C ns t ahsr ack hold to s data master read from slave 300 C C ns t sdhr s data hold master read from slave 300 C 650 ns t sdsr s data setup master read from slave 300 C C ns
mt9d115 ds rev. e pub. 4/15 en 15 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels provide data for the offset-correction algorithms (black level control). the sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain settings. these registers are controlled by the firmware and can be accessed through a two-wire serial interface. register values writ ten to the sensor core can be overwritten by firmware. the output from the core is a bayer pattern , where alternate rows are a sequence of either green and red pixels or blue and gree n pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. a flash strobe output signal is provided to al low an external xenon or led light source to synchronize with the sensor exposure time. figure 7: sensor core block diagram pixel array the sensor core uses a bayer color pattern (see figure 8). the even-numbered rows contain green and red pixels. the odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels. odd-numbered columns contain red and green pixels. sensor core active -pixel sensor (aps ) array timing and control control registers gr and gb channel red and blue channel analog processing adc pll digital processing 10-bit data out gr and gb red and blue gr and gb red and blue
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 16 ?semiconductor components industries, llc,2015. figure 8: pixel color pattern detail (top right corner) default readout order by convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner. this reflects the actual layout of th e array on the die. when the sensor is oper- ating in a system, the active surface of the sensor faces the scene (see figure 9). when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced. by convention, data from the sensor is shown with the first pixel read out in the case of the sensor core in the top left corner. figure 9: imaging a scene analog processing analog readout channel the sensor core features an analog read out channel, (see figure 7 on page 15). the readout channel consists of a gain stage, a sample-and-hold stage with black level cali- bration capability, and a 10-bit adc. b gr b gr b g2 r gb r gb b gr b gr b g2 r gb r gb b gr b gr b g2 r g2 r g2 black pixels column readout direction . . . ... row readout direction first clear pixel lens pixel (0,0) row readout order column readout order scene sensor (rear view)
mt9d115 ds rev. e pub. 4/15 en 17 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture gain options the mt9d115 provides per-color gain control as well as the option of global gain control. the per-color and global gain contro l can be used interchangeably. a write to a global gain register is aliased as a write of the same data to the four associated color-dependent gain registers. integer digital gains in the range 0?7 can be pr ogrammed. a digital gain of 0 sets all pixel values to 0 (the pixel data will simply repres ent the value applied by the pedestal block). gain settings are updated in every frame by the mcu auto functions such as awb, ae, and fd. to make manual adjustments to gain settings, the mcu automatic exposure and automatic white balance adjustment features must be disabled. integration time the integration time (exposure) of the mt9d11 5 is controlled by variables. while coarse integration time controls the integration durati on in terms of row times, fine integration time allows for sub-row times accuracy in terms of pixel clocks. integration time is updated in every frame by the mcu auto feature. disable the mcu auto features to make manual adjustments to integration time. because of the basic operation of the electronic roller shutter (ers), it is not advisable to set an integration time that is greater than the frame time. it is not necessary to reprogram the frame time on the mt9d115 to make longer integra- tion times available because the frame time adjusts automatically. however, long inte- gration times increase the likelihood of image degradation because of increased accumulation of dark current. if the integration time is changed while fv is asserted for frame n , the first frame output using the new integration time is frame ( n + 2). the sequence is as follows: 1. during frame n , the new integration time is held in the pending register. 2. at the start of frame ( n + 1), the new integration time is transferred to the live register. integration for each row of frame ( n + 1) has been completed using the old integration time. 3. the earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame ( n + 1). 4. when frame ( n + 2) is read out, it will have b een integrated using the new integration time. if the integration time is changed on successive frames, each value written will be applied for a single frame; the latency betwee n writing a value and it affecting the frame readout remains at two frames. when the integration time and the gain are ch anged at the same time, the gain update is held off by one frame so that the first fram e output with the new integration time also has the new gain applied. external generated master clock if application does not use pll, then the cl ock bypass bit in r0x0014 must be set before exiting soft standby state as follows: 1. write 0x25f9 to r0x0014 to set clock bypass bit 2. delay min. of 100 ms 3. write 0x4028 to r0x0018 to exit from soft standby state 4. after successful exit from soft standby st ate, disable the clock bypass bit by writing 0x21f9 to r0x0014
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 18 ?semiconductor components industries, llc,2015. pll-generated master clock the pll can generate a master clock signal whose frequency is up to 85 mhz (input clock from 6 mhz through 54 mhz). pll setup because the input clock frequency is unknow n, the sensor starts up with the pll disabled. the pll takes time to power up. duri ng this time, the beha vior of it s output clock signal is not guaranteed. the pll output frequency is determined by two constants, m and n, and the input clock frequency. (eq 1) digital processing readout options the sensor core supports different readout opti ons to modify the image before it is sent to the ifp. the readout can be limited to a sp ecific window of the original pixel array. for preview modes, the sensor core suppor ts both skipping and pixel averaging in xandy directions. by changing the readout direction the image can be flipped in the vertical direction and/or mirrored in the horizontal direction. window size the image output size is set with register s x_addr_start, x_addr_end, y_addr_start, and y_addr_end. the edge pixels in the 1600 x 1200 array are present to avoid edge defects and should not be included in the visible wi ndow. binning will change the image output size. readout modes horizontal mirror when the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed, so that re adout starts from x_addr_end and ends at x_addr_start. figure 10 shows a sequence of 6 pixels being read out with normal readout and reverse readout. the soc corrects fo r this change in sensor core output. vco fin 2 ? m ? n 1 + ---------------- ------------- = pll output frequency vco p 11 + --------------- - =
mt9d115 ds rev. e pub. 4/15 en 19 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture figure 10: six pixels in normal and column mirror readout modes vertical flip when the sensor is configured to flip the image vertically, the order in which pixel rows are read out is reversed, so that row readou t starts from y_addr_end and ends at y_ad- dr_start. figure 11 shows a sequence of six ro ws being read out with normal readout and reverse readout. the soc corrects for this change in sensor core output. figure 11: six rows in normal and row mirror readout modes column and row skip the sensor core supports subsampling. su bsampling reduces the amount of data processed by the analog signal chain in the sensor and thereby allows the frame rate to be increased. this reduces the amount of ro w and column data processed and is equiva- lent to the skip2 readout mode provided by earlier on semiconductor image sensors. set the proper image output and crop sizes before enabling subsampling. figure 12: eight pixels in normal and column skip 2x readout modes d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) reverse readout g2 (9:0) r2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) d out [9:0] frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out [9:0] reverse readout row4 (9:0) row5 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) row0 (9:0) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) d out [9:0] line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) r2 (9:0)
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 20 ?semiconductor components industries, llc,2015. pixel readouts figures 13 through figure 16 on page 22 show a sequence of data being read out with no skipping, with x_odd_inc = 3 and y_odd_inc = 1 , with x_odd_inc = 1 and y_odd_inc = 3 , and with x_odd_inc = 3 and y_odd_inc = 3 . figure 13: pixel readout (no skipping) x incrementing y incrementing
mt9d115 ds rev. e pub. 4/15 en 21 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture figure 14: pixel readout (x_odd_inc = 3, y_odd_inc = 1) figure 15: pixel readout (x_odd_inc = 1, y_odd_inc = 3) x incrementing y incrementing x incrementing y incrementing
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 22 ?semiconductor components industries, llc,2015. figure 16: pixel readout (x_odd_inc = 3, y_odd_inc = 3) programming restrictions when skipping when skipping is enabled as a viewfinder mode, and the sensor is switched back and forth between full resolution and skipping, keep line_length_pck constant. this allows the same integration times to be used in each mode. when subsampling is enabled, it might be necessary to adjust the x_addr_end and y_ad- dr_end settings. the values for these registers must correspond with rows/ columns that form part of the subsampling sequence. use the following rules to make the adjustment. (eq 2) (eq 3) table 6 shows the row address sequencing for normal and subsampled (with y_odd_inc = 3 ) readout. the same sequencing applies to column addresses for subsam- pled readout. because the subsampling sequence only reads half of the rows and columns, there are two possible subsampling sequences, depending upon the alignment of the start address. x incrementing y incrementing remainder = (addr_end addr_start ? 1 ? and 4 + if (remainder == 0) addr_end = addr_end 2 ?
mt9d115 ds rev. e pub. 4/15 en 23 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture binning the mt9d115 sensor core supports 2 x 1 and 2 x 2 analog binning (c olumn binning, also called x-binning and row/column binning, also called xy-binning). binning has many of the same characteristics as subsampling. ho wever, because binning gathers image data from all pixels in the active window, rather than from a subset of pixels, it achieves supe- rior image quality and avoids the aliasing artifa cts that can be a characteristic side effect of subsampling. enable binning by selecting the appropriate subsampling settings ( x_odd_inc = 3 and y_odd_inc = 1 for x-binning, x_odd_inc = 3 and y_odd_inc = 3 for xy-binning) and setting the appropriate binning bit in read_mode regi ster. as for subsampling, x_addr_end and y_addr_end might require adjustment when binning is enabled. the effect of the different subsampling settings is shown in figure 17 and in figure 18 on page 24. figure 17: pixel readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1) table 6: row address sequencing (sampling) normal subsampled sequence 1 subsampled sequence 2 00 no data 11 no data 2no data 2 3no data 3 44 no data 55 no data 6no data 6 7no data 7 y incrementing x incrementing
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 24 ?semiconductor components industries, llc,2015. figure 18: pixel readout (x_odd_inc = 3, y_odd_inc = 3, x_ybin = 1) binning limitations binning requires a different se quencing of the pixel array and imposes different timing limits on the operation of the sensor. in pa rticular, xy-binning re quires two read opera- tions from the pixel array for each line of output data, which has the effect of increasing the minimum line blanking time. as a result, when xy-binning is enabled, some of the programming limits declared in the parameter limit registers are no longer valid. in addition, the default values for some of the manufacturer-specific registers need to be reprogrammed. none of these adjust- ments are required for x-binning. the sensor must be taken out of streaming mode before switching between binned and non-binned operation. the row addresses for various binning modes are shown in table 7. raw data format the sensor core image data is read out in a progressive scan. valid image data is surrounded by horizontal blanking and vert ical blanking, (see figure 19). the amount of horizontal blanking and vertical blanking is programmable. lv is high during the shaded region of the figure. table 7: row address sequencing (binning) normal binning sequence 1 binning sequence 2 00, 2 no data 11, 3 no data 2no data 2, 4 3no data 3, 5 44, 6 no data 55, 7 no data 6no data 6, 8 7no data 7, 9 y incrementing x incrementing
mt9d115 ds rev. e pub. 4/15 en 25 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture figure 19: valid image data raw data timing the sensor core output data is synchronized with the pixclk output. when lv is high, one pixel?s data is output on the 10-bit d out output bus every pixclk period. by default, the pixclk signal runs at the same frequency as the master clock, and its falling edges occur one-half of a master clock pe riod after transitions on lv, fv, and d out [9:0] (see figure 20). this allows pixclk to be us ed as a clock to sample the data. pixclk is continuously enabled, even during the blanking period. figure 20: pixel data timing example p 0,0 p 0,1 p 0,2 ................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 ................................p 1,n-1 p 1,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 p m-1,0 p m-1,1 .........................p m-1,n-1 p m-1,n p m,0 p m,1 .........................p m,n-1 p m,n 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ............. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ................................ 00 00 00 00 00 00 ................................ 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking p 0 (9:0) p 1 (9:0) p 2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking line_valid pixclk d out 0-d out 9
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 26 ?semiconductor components industries, llc,2015. input interface to image flow processor the input interface to the ifp is the front end of the ifp, in which it will choose between the sensor core output or a test pattern ge nerator output. during normal operation, a stream of raw bayer image data from the sens or is continuously fed into the ifp. for testing purposes, the test generator output is selected. the generator provides a selec- tion of test patterns suffici ent for basic testing of the ifp. program variable (id=7, offset=0x66) followed by refresh command to the sequencer in order to access different test patterns (see figure 21). depending on which test pattern has been selected, the user might need to program additional registers in order to see the intended effects. figure 21: available test patterns test pattern registers/variables example flat field vertical ramp mode_common_ mode_settings test_mode (id=7, offset=0x66)=2 color bar vertical stripes pseudo-random horizontal stripes mode_common settings_test_mode (id=7, offset=0x66)=1 test_pxl_red (r0x0102) = 0x1ff test_pxl_g1 (r0x0104) = 0x1ff test_pxl_g2 (r0x0106) = 0x1ff test_pxl_blue (r0x0108) = 0x1ff mode_common_ mode_settings test_mode (id=7, offset=0x66)=3 mode_common settings_test_mode (id=7, offset=0x66)=4 test_pxl_red (r0x0102) = 0x1ff test_pxl_g1 (r0x0104) = 0x17d test_pxl_g2 (r0x0106) = 0x000 test_pxl_blue (r0x0108) = 0x000 mode_common_mode settings_test_mode (id=7, offset=0x66)=5 mode_common settings_test_mode (id=7, offset=0x66)=6 test_pxl_red (r0x0102) = 0x1ff test_pxl_g1 (r0x0104) = 0x17d test_pxl_g2 (r0x0106) = 0x000 test_pxl_blue (r0x0108) = 0x000
mt9d115 ds rev. e pub. 4/15 en 27 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture image flow processor most ifp functions can be contro lled directly by the mcu. th e external host will control it indirectly through the driver variables. ifp processing can be broken into three different phases: pixel reconstruction, color rendering/statistics collection, and digital scaling/output format. figure 22 shows a simplified ifp block diagram and the operating color space at each processing phase. figure 22: ifp block diagram pixel reconstruction (lens shading correction) first black level subtraction and digital gain image stream processing starts with black level subtraction and multiplication of all pixel values by a programmable digital gain. both operations can be independently set to separate values for each color channel (r, gr, gb, b). independent color channel digital gain can be adjusted with registers. independent color channel black level adjust- ments can also be made. if the black level su btraction produces a negative result for a particular pixel, the value of this pixel is set to ?0.? pixel array adc test pattern generator black level subtraction color correction aperture correction gamma correction (10-to-8 lookup ) color kill scaler output formatting yuv to rgb mipi raw data bypass 8-bit rgb raw 10 8-bit rgb 8-bit yuv output fifo parallel output serial output output format rgb to yuv statistics engine digital gain control, shading correction defect correction, nosie reduction, color interpolation pixel reconstruction digital scaling/output format color rendering/statistics collection
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 28 ?semiconductor components industries, llc,2015. shading correction (sc) lenses tend to produce images whose bright ness is significantly attenuated near the edges. other factors also cause fixed pattern signal gradients in images captured by image sensors. the cumulative result of all factors is known as image shading. the mt9d115 has an embedded shading correcti on module that can be programmed to counter the shading effects on each individual r, gb, gr, and b color signal. the correction function color-dependent solutions are calibrated using the sensor, lens system, and an image of an evenly illuminated, featureless grey cali bration field. the color correction functions can be derived from the resulting image. the correction functions can then be appl ied to each pixel value to equalize the response across the image as follows: (eq 4) where p are the pixel values and f is the color dependent correction functions for each color channel. defect correction the ifp performs continuous de fect correction that can mask pixel array defects such as high dark-current (hot) pixels and pixels that are darker or brighter than their neighbors due to photoresponse nonuniformity. the modu le is edge-aware with exposure that is based on configurable thresholds. the thre sholds are changed continuously based on the brightness of the current scene. noise reduction noise reduction can be enabled or disabled. thresholds can be set through register settings. color interpolation and edge detection in the raw data stream fed by the sensor core to the ifp, each pixel is represented by a 10-bit integer number, which can be considered proportional to the pixel's response to a one-color light stimulus, red, green, or blue , depending on the pixel's position under the color filter array. initial data processing steps?up to and including the defect correc- tion?preserve the one-color-per-pixel nature of the data stream. after the defect correc- tion, the data stream must be converted to a three-colors-per-pixel stream appropriate for standard color processing. the conversion is done by an edge-sensitive color inter- polation module. the module pads the incomp lete color information available for each pixel with information extracted from an appropriate set of neighboring pixels. the algorithm used to select this set and extrac t the information seeks the best compromise between preserving edges and filtering out high frequency noise in flat field areas. the edge threshold can be set through register settings. aperture correction to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through variable settings. p corrected (row,col)=p sensor (row,col)*f(row,col)
mt9d115 ds rev. e pub. 4/15 en 29 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture color rendering/statistics collection (color correction) color correction to achieve good color fidelity of the ifp outp ut, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the three components of the resulting color vector are all sums of three 10-bit numbers. because such sums can have up to 12 significant bits, the bit width of the image data stream is widened to 12 bits per color (36 bits per pixel). the color correction matrix can be programmed by the user or automatically selected by the awb algorithm implemented in the ifp. ideally, color correction should produce output colors that are independent of the spectral sensitivity and color crosstalk characteristics of the image sensor. the optimal values of the color correction matrix elements depend on those sensor characteristics and on the sp ectrum of light incident on the sensor. the color correction variab les can be adjusted th rough register settings. image cropping by configuring the cropped and output wind ows to various sizes, different zooming levels (for example 4x, 2x, and 1x) can be achieved. the location of the cropped window is also configurable so that panning is al so supported. a separate cropped window is defined for context a and context b. in both contexts, the height and width definitions for the output window must be equal to or smaller than the cropped image. gamma correction the gamma correction curve (see figure 23 on page 30) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. the abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. the 8-bit ordinates are programmable through ifp registers. the mt9d115 ifp includes a block for gamma co rrection that can adjust its shape based on brightness to enhance the performanc e under certain lighting conditions. two custom gamma correction tables can be uploaded, one corresponding to a brighter lighting condition, the other corresponding to a darker lighting condition. at power-up, the ifp loads the two tables with default values. the final gamma correction table used depends on the brightness of the scene and ca n take the form of either uploaded tables or an interpolated version of the two tables . a single (non-adjusting) table for all condi- tions can also be used.
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 30 ?semiconductor components industries, llc,2015. figure 23: gamma correction curve color kill a color kill circuit is included to remove high or low light color artifacts. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proporti onally to the difference between their lumi- nance and the threshold. digital scaling/output format special effects special effects like negative image, sepia, or black and white can be applied to the data stream at this point. these effects ca n be enabled and selected by registers. rgb to yuv conversion for further processing, the data is converted from rgb color space to yuv color space. yuv color filter as an optional processing st ep, noise suppression by one-dimensional low-pass filtering of y and/or uv signals is possible. a 3- or 5-tap filter can be selected for each signal. image scaling the ifp includes a scaler module to ensure that the size of images output by the mt9d115 can be tailored to the needs of all us ers. when enabled, this module performs rescaling of incoming images?shrinks them to arbitrarily select ed width and height without reducing the field of view an d without discarding any pixel values. the scaler performs pixel binning?divides each input image into rectangular bins corresponding to individual pixels of the desired output image, averages pixel values in these bins, and assembles the output image from the bin averages. pixels lying on bin boundaries contribute to more than one bin average; their values are added to bin-wide sums of pixel values with fractional weights. the entire procedure preserves all image information that can be included in the do wnsized output image and filters out high frequency features that could cause aliasing. use the image cropping and scaler module together to implement a digital zoom and pan. if the scaler is progra mmed to output images smaller than images coming from the sensor core, zoom effect can be produced by cropping the latter from their maximum gamma correction 0 50 100 150 200 250 300 0 1000 2000 3000 4000 input rgb, 12-bit output rgb, 8-bit 0.45
mt9d115 ds rev. e pub. 4/15 en 31 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture size down to the size of the output images . the ratio of these two sizes determines the maximum attainable zoom factor. for ex ample, a 1600 x 1200 image rendered on a 250 x 150 display can be zoomed up to eight times, because 1280/160 = 1024/128 = 8. a panning effect can be ac hieved by fixing the size of the crop- ping window and moving it around the pixel array. yuv-to-rgb/yuv conversion and output formatting the yuv data stream emerging from the scal ing module can either exit the color pipe- line as-is or be converted before exit to an alternative yuv or rgb data format. color conversion formulas y'u'v' this conversion is itu-r bt .601 scaled to make yuv range from 0 through 255. this setting is recommended for jpeg en coding and is the most popular. (eq 5) (eq 6) (eq 7) there is an option where 128 is not added to u'v'. y'cb'cr' using srgb formulas the mt9d115 implements the srgb standard. this option provides ycbcr coefficients for a correct 4:2:2 transmission. note: 16 < y?< 235; 16 < cb < 240; 16 < cr < 240; and 0 ? rgb ? 255 (eq 8) (eq 9) (eq 10) y'u'v' using srgb formulas similar to the previous set of formulas, bu t has yuv spanning a range of 0 through 255. (eq 11) (eq 12) (eq 13) there is an option to disable adding 128 to u'v'. the reverse transform is as follows: (eq 14) (eq 15) (eq 16) y ? 0.299 r ? 0.587 g ? 0.114 b ? ? + ? + ? = u ? 0.564 (b ? y ? ? ? 128 + ? = v ? 0.713 (r ? y ? ? ? 128 + ? = y ? (0.2126 r ? 0.7152 g ? 0.0722 b ? ? (219 256) + 16 ? ? ? + ? + ? = cb ? 0.5389 (b ? y ? ? (224 256) + 128 ? ? ? ? = cr ? 0.635 (r ? y ? ? (224 256) + 128 ? ? ? ? = y ? 0.2126 r ' 0.7152 g ' 0.0722 b ' ? + ? + ? = u ? 0.5389 b ' y ' ? ?? 128 0.1146 ? r ' 0.3854 g ' 0.5 b ' 128 + ? + ? ? ? = + ? = v ? 0.635 (r ? y ? ? ? ? 128 0.5 r ' 0.4542 g ' 0.0458 b ' 128 + ? ? ? ? ? = + = r ? y 1.5748 v 128 ? ?? ? + = g ? y 0.1873 (u 128 ? ? ? ? 0.4681 (v 128) ? ? ? = b ? y 1.8556 (u 128) ? ? + =
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 32 ?semiconductor components industries, llc,2015. output interface from ifp the output interface contains parallel image bus, mipi serial bus interfaces, and walking 1s connectivity test generator. parallel and mipi output the user can select to use either the serial mipi output or the 10-bit parallel output to transmit the data. only one of the output modes can be used at any time. the parallel output can be used with an ou tput fifo whose memory is shared with the mipi output fifo to retain a constant pixe l output clock independ ent from the scaling factor. when scaling the image or skipping lines, the data would be generated in bursts and the pixel clock would turn on and off in intervals, which might lead to emi problems. the output fifo will group all active pixel data together so the pixel clock can be run at a constant speed. the mipi output transmitter implements a serial differential sub-lvds transmitter capable of up to 512 mb/s. it supports multiple formats, error checking, and custom short packets. the mipi clock is defi ned as half the data rate frequency. the virtual channel could be used by host mipi rx circuits to differentiate between preview and capture image data if the fw changes the channel number when switching between contexts. the host cannot adequately time this switching of contexts and so cannot use channel number in this way without fw support. the hardware supports a configurable mipi vi rtual channel in the mipi control register (r0x3400). firmware provides two variables th at allow the mipi virtual channel to be changed according to context (preview/a, capture/b). the host can specify what channel is used for which context through these variables. note: data will be packed as raw8 if the data type specified does not match any of the above data types. table 8: data formats supported by mipi interface data format data type yuv 422 8-bit 0x1e 565rgb 0x22 555rgb 0x21 444rgb 0x20 raw8 0x2a raw10 0x2b
mt9d115 ds rev. e pub. 4/15 en 33 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor architecture output format and timing yuv/rgb output yuv or rgb data can be output either directly from the output formatting block or through a fifo buffer with a capacity of 1024 bytes. this size is large enough to hold one-fourth of a scan line at full resolution. bu ffering of data is a way to equalize the data output rate when image scaling is used. scaling produces an intermittent data stream consisting of short high-rate bursts separated by idle periods. high pixel clock frequency during bursts may be undesirable due to emi concerns. figure 24 shows the output timing of a yuv/rg b scan line when a scaled data stream is equalized by buffering or when no scaling takes place. the pixel clock frequency remains constant during each lv high period. scaled data is output at a lower frequency than full size frames, which helps to reduce emi. figure 24: timing of full frame data or scaled data passing through the fifo yuv/rgb data ordering the mt9d115 supports swapping ycbcr mode (see table 9). the rgb output data ordering in default mode is shown in table 10. the odd and even bytes are swapped when luma/chroma swap is enabled. r and b channels are bitwise swapped when chroma swap is enabled. table 9: ycbcr output data ordering mode data sequence default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i table 10: rgb ordering in default mode mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 565rgb odd r 7 r 6 r 5 r 4 r 3 g 7 g 6 g 5 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3
mt9d115: 1/5-inch soc digital image sensor architecture mt9d115 ds rev. e pub. 4/15 en 34 ?semiconductor components industries, llc,2015. 10-bit bypass output raw 10-bit bayer data from the sensor core ca n be output in bypass mode in two ways: 1. using eight data output signals (d out [7:0]) and gpio[1:0]. the gpio signals are the lowest two bits of data. 2. using only eight signals (d out [7:0]) and a special 8 + 2 data format, shown in tabl e 11 . fifo during normal pipeline operation, the output data rate is determined by a number of factors: input image size, degree of scaling, and sensor operation mode. as these param- eters change during normal sensor operation, output frequency changes. this output frequency may generate rf noise, interfering with the mobile device. by using an output fifo to maintain a constant output clock frequency, noise is easily filtered out. the fifo accumulates data and after a certain number of bytes are stored, it will output them in a single burst, making sure that th e data rate within the burst remains constant. this approach utilizes a free-running clock, thus making possible minimal rf interfer- ence. 555rgb odd 0 r 7 r 6 r 5 r 4 r 3 g 7 g 6 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3 444xrgb odd r 7 r 6 r 5 r 4 g 7 g 6 g 5 g 4 even b 7 b 6 b 5 b 4 0 0 0 0 x444rgb odd 0 0 0 0 r 7 r6 6 r 5 r 4 even g 7 g 6 g 5 g 4 b 7 b 6 b 5 b 4 table 11: 2-byte rgb format byte bits used bit sequence odd bytes 8 data bits d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 d 1 d 0 table 10: rgb ordering in default mode (continued) mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
mt9d115 ds rev. e pub. 4/15 en 35 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor control functions control functions sequencer: camera operating system the sequencer is a finite state machine that controls the general operations of the camera and switching between operating modes. camera operation is organized in states such as enter preview, preview, leave preview, enter capture, and capture. the sequencer carries out a number of commands such as run, go preview, go capture, refresh, and refresh mode. the current state of the sequencer is indicated in a variable seqr.state. to execute a command, the user must set a particular command number in the variable seqr.cmd . on semiconductor recommends that the external host monitor seqr.state to know when to change resolution or capture frames. each state has its configuration; therefore, th e user should set up the state configuration to customize the camera configuration be fore executing the corresponding program such as go to capture. a typical camera operating scenario is: 1. configure mode variables after hardware reset. 2. configure preview mode. 3. execute sensor refresh program. 4. run in preview until shutter button is pressed. 5. capture a frame.
mt9d115: 1/5-inch soc digital image sensor control functions mt9d115 ds rev. e pub. 4/15 en 36 ?semiconductor components industries, llc,2015. figure 25: sequencer finite state machine note: any state except init can transition to stan dby state by either hard standby or soft standby. mode: context information the mode driver reduces integration efforts by managing most aspects of switching the two contexts. it remembers vital register values for each image acquisition context and loads these values to the appropriate regi sters in the ifp upon context switching. for the mode driver variables to take effect, the user changes the variable values in the mode driver (id = 7). upon the next mode change or sequencer's refresh command, these driver variable values will be loaded to the appropriate physical sensor core and ifp registers. the image processing will take the new values at the beginning of the next frame acquired. to control the output image size, the user ca n modify the mode driver variables such as output_width_a , output_height_a , output_width_b , and output_height_b . the mode driver will automatically apply any appropriat e downscaling filter to achieve this output image size as well as update the watermark of the output fifo. it is important to set up the sensor core to output an image equal to or larger than the crop window size, which in turn is equal to or larger than the desired output image size. preview capture init chg mode to preview enter preview leave preview chg mode to capture enter capture go preview go capture go preview or go capture standby go preview go capture refresh mode refresh mode refresh or run refresh or run standby 1 standby por leave capture 0x0018[2] = 1 0x0018[2] = 0 standby
mt9d115 ds rev. e pub. 4/15 en 37 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor camera functions camera functions simple rule-based auto exposure the ae algorithm performs automatic adjustments of the image brightness by controlling exposure time and analog gains of the sensor core as well as digital gains applied to the image. auto exposure is implemented by a firmware (fw) driver that analyzes image statistics collected by the exposure measurement engine, makes a decision, and programs the sensor core and color pipeline to achieve the desired exposure. the measurement engine subdivides the image into 16 windows organized as a 4 x 4 grid. an ae algorithm mode is available: average brightness tracking (abt). the abt ae uses a constant average tracking algorithm where a target brightness value is compared to a current brightness value, and the gain and integration time are adjusted accordingly to meet the target requirement. ae driver drt exposure mode is activated during preview. this mode can also be enabled during video capture mode. the drt exposure mode relies on the statistics engine to track speed and amplitude of the change of the ov erall luminance in the selected windows of the image. backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. other algorithm features include the rejection of fast fluctuations in illumina tion (time averaging), control of speed of response, and control of the sensitivity to the small changes. while the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters. the driver calculates image brightness based on average luma values received from 16 programmable equal-size rectangular windows forming a 4 x 4 grid. in preview mode, 16 windows are combined in two segments: central and peripheral. the central segment includes four central windows. all remaining windows belong to the peripheral segment. scene brightness is calculated as average luma in each segment taken with certain weights. the driver changes ae parameters (integration time, gains, and so on) to drive bright- ness to the programmable target. the value of the single step approach to the target value can be controlled. to avoid unwanted reaction of ae on small fluctuations of scene brightness or momen- tary scene changes, the ae driver uses a temporal filter for luma and a threshold around the ae luma target. the driver changes ae para meters only if the filtered luma is larger than the ae target step and push es the luma beyond the threshold. evaluative algorithm a scene-evaluative ae algorithm is availabl e for use in snapshot mode. the algorithm performs scene analysis and classification wi th respect to its brightness, contrast, and composure and then decides to increase, decrease, or keep the original exposure target. it makes the most difference for backlight and bright outdoor conditions.
mt9d115: 1/5-inch soc digital image sensor camera functions mt9d115 ds rev. e pub. 4/15 en 38 ?semiconductor components industries, llc,2015. accelerated settling during overexposure the ae speed is direction-dependent. transi tioning from overexposure to target can take more time than transitioning from underexposure. the ae driver has a mode that speeds up ae for overexposed scenes. the ae driver counts the number of ae wind ows whose average brightness is equal to or greater than some value, 250 by default. for a scene that has saturated regions, the average luma is underestimated because of signal clipping. the driver compensates underestimation by a factor that can be defined. exposure control to achieve the required amount of exposure, the ae driver adjusts the sensor integration time, gains, adc reference, and ifp digital gains. in addition, ae _base_target (id = 2, offset = 0x4f) is available for the user to adjust the overall brightness of the scene. flicker detection and avoidance flicker occurs when the integration time is not an integer multiple of the period of the light intensity. the automatic flicker detection block does not compensate for the flicker, but rather avoids it by detecting the flicke r frequency and adjusting the integration time. to reject flicker, integration time is typicall y adjusted in increments of steps. the incre- mental step specifies the duration in row times equal to one flicker period. thus, flicker is rejected if integration time is kept to an integral factor of the flicker period. flicker cannot be avoided for integration time s below the light intensity period (10ms for 50hz environment). flicker shows up in the image as horizontal ba rs that roll up or down. the mcu looks for these rolling bars using a thin horizontal window, which outputs luma average and is applied to 48 points in the upper half of the image. the mcu repeats the same sampling on the next frame; 48 samples from the previous frame are subtracted from corre- sponding samples from the current frame. skipping more frames between subtraction can be set by a variable. the mcu then smooths the 48 sampling points, applies an amplitude threshold to avoid false detection, and looks at the resulting waveform. if flicker is present, the waveform should ha ve a frequency within the search range. assuming the flicker power is a sine wave, subtracting two frames results in: (eq 17) which is a cosine wave of the original frequency. sin(wt) sin(wt ? a) 2 sin(a 2) cos(wt (a 2 ?? ? + ? ? ? = +
mt9d115 ds rev. e pub. 4/15 en 39 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor camera functions auto white balance the mt9d115 has a built-in awb algorithm designed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. the algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a driver performing the selection of the optimal color correc- tion matrix, digital gains, and sensor core an alog gains. while default settings of these algorithms are adequate in most situations, the user can reprogram the base color correction matrices, place limits on color channel gains, and control the speed of both matrix and gain adjustments. flash to take a snapshot, the user must send a command that changes the context from preview to snapshot. the typical sequence of events after this command is: 1. the camera might turn on its led flash, if it has one and is required to use it. with the flash on, the camera exposure and white balance are automatically adjusted to the changed illumination of the scene. 2. the camera captures one or more frames of desired size. a camera equipped with a xenon flash strobes while capturing images . when the images are captured, the cam- era automatically returns to context a and resumes running in preview mode. note: this sequence of events can take up to 10 frames. histogram: dark level adjustment s, low light and tonal controls the histogram driver continually works to re duce image flare and continually analyzes input image histogram and dynamically adjusts the black level. when flare is present (hence, the histogram does not contain dark to nes), it causes the driver to subtract a higher black level, thus regaining the lost contrast. in certain situations, the scene may contain no dark tones without flare. the hi stogram driver cannot distinguish this situa- tion and alters the black level just the same, causing the image to have more contrast, which looks acceptable in many situations. besides black level adjustments and low light scene parameters, this driver also contains variables for the preloaded and custom gamma tables.
mt9d115: 1/5-inch soc digital image sensor optics mt9d115 ds rev. e pub. 4/15 en 40 ?semiconductor components industries, llc,2015. optics figure 26 shows the cra versus image height. note: on semiconductor recommends a 670nm ir cut filter to achieve the best image qual- ity; however, a 650nm ir cut filter is acceptable. figure 26: cra vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 0 0.000 0.00 5 0.088 2.22 10 0.175 4.39 15 0.263 6.54 20 0.350 8.68 25 0.438 10.79 30 0.525 12.86 35 0.613 14.87 40 0.700 16.78 45 0.788 18.56 50 0.875 20.17 55 0.963 21.59 60 1.050 22.79 65 1.138 23.74 70 1.225 24.43 75 1.313 24.85 80 1.400 25.02 85 1.488 24.96 90 1.575 24.71 95 1.663 24.31 100 1.75 23.85 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00 26.00 28.00 30.00 0 10 20 30 40 50 60 70 80 90 100 110 image height (%) cra (deg)
mt9d115 ds rev. e pub. 4/15 en 41 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes power modes power application sequence on semiconductor recommends the followi ng sequence to maintain low power consumption during this process: caution applying power to analog supplies prior to applying digital and io supplies or any other fail- ure to follow the correct power up sequence ma y result in high current consumption and die heating. this can potentially result in performance and reliability issues. 1. ensure that standby is de-asserted and reset_bar is asserted. 2. apply io supply (v dd _io) to the image sensor and wait for the io supply to be stable. 3. minimum of 1 ms after io supply is stab le, apply digital supply to the image sensor and wait. 4. enable extclk and wait for th e extclk signal to stabilize. 5. de-assert reset_bar for a minimum of 10 extclk cycles. 6. after asserting the reset_bar, apply analog supplies (v aa , v aa _pix, and v dd _pll) to the image sensor. 7. after 6000 extclk cycles from the end of step 6, the image sensor will be in soft standby state. 8. communication with the sensor thorough two-wire serial interface can start 1 ext- clk after step 7. in cases where the recommended procedure cannot be followed, the following condi- tion would affect the sensor?s power co nsumption during th e power application sequence: ? when analog supplies are applied prior to the digital and io supplies, high current consumption on the analog supplies may be present.
mt9d115: 1/5-inch soc digital image sensor power modes mt9d115 ds rev. e pub. 4/15 en 42 ?semiconductor components industries, llc,2015. figure 27: power application sequence timing power-on reset the sensor includes a power-on reset feature that initiates a reset upon power-up. even though this feature is included on the device, it is advised that the user still manually assert a hard reset upon power-up. the mt9d115?s por circuit generates internal reset only and it will not generate the external reset signal through reset_bar. the por circuit requires v dd ramp time to be less than 10s. if the ramp time is longer than 10s, the por operation is not guaran teed and external reset must be used. the por circuit will generate an internal reset when v dd falls below 1.25v (typical) for 1s (typical) period, as shown in figure 28 and described in table 13. table 12: power application sequence timing parameters symbol min typ max units delay from stable reset_bar, standby signals to vddio power start t0 0 C C ns delay from stable v dd _io to v dd start t1 1 C C ms delay from stable v dd power to extclk start t2 0 C C ns delay from extclk start to stable extclk t3 1 C C extclk reset_bar pulse width t4 10 C C extclk delay from reset_bar de-asserting to analog power supplies start t5 1 C C extclk delay from analog power stable to soft standby mode t6 6000 C C extclk delay from soft standby mode to first two-wire bus transaction t7 1 C C extclk t0 t4 standby t1 t2 t3 reset_bar extclk v dd _io v dd v aa _, v aa _pix, v dd _pll two-wire serial bus t5 t6 t7
mt9d115 ds rev. e pub. 4/15 en 43 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes the por circuit reset and extern al reset_bar signals are gated together to generate an internal reset for mt9d115. figure 28: internal power-on reset table 13: por parameters symbol definition min typ max unit t 1 minimum v dd spike width below v trig _ falling considered to be a reset C 1 C ? s v trig _ rising v dd rising trigger voltage 1.15 1.4 1.55 v v trig _ falling v dd falling trigger voltage 1 1.25 1.45 v v dd t 1 v trig_rising v trig_falling
mt9d115: 1/5-inch soc digital image sensor power modes mt9d115 ds rev. e pub. 4/15 en 44 ?semiconductor components industries, llc,2015. hard reset the mt9d115 enters the reset state when th e external reset_bar signal is asserted low, as shown in figure 29 and described in table 14. all of the output signals will be in high-z state except the mipi outp uts, which will be driven low. figure 29: hard reset operation table 14: hard reset symbol definition min typ max unit t 1 reset_bar pulse width 100 C C extclk cycles t 2 active extclk required after reset_bar asserted 10 C C t 3 active extclk required before reset_bar de-asserted 10 C C t 4 maximum internal boot time C C 6000 extclk reset reset_bar mode t 2 t 3 t 1 internal boot time s data entering standby mode and two-wire serial interface is ready t 4 all outputs data active after programming by host processor data active
mt9d115 ds rev. e pub. 4/15 en 45 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes soft reset the host processor can reset the mt9d115 usin g the two-wire serial interface by writing to sysctl 0x001a. two types of soft reset ar e available. sysctl 0x 001a[0] is used to reset the mt9d115, which is similar to external reset_bar signal. 1. set sysctl 0x001a1:0] to 0x3 to initiate internal reset cycle. 2. wait 6000 extclk cycles. 3. reset sysctl 0x001a[0] to 0x0 for normal operation. figure 30: soft reset operation table 15: soft re set signal timing symbol parameter min typ max unit t 1 maximum soft reset time C C 6000 extclks ext clk t 1 s data mode write soft reset command reseting registers registers reset to default values sclk
mt9d115: 1/5-inch soc digital image sensor power modes mt9d115 ds rev. e pub. 4/15 en 46 ?semiconductor components industries, llc,2015. power removal sequence on semiconductor recommends using the following method to remove the power supplies from the image sensor. 1. put the image sensor into either hard standby or soft standby mode as described in ?standby modes? on page 47. 2. remove all digital and analog supplies. during step 2, the digital and analog supplies can be removed safely either one by one or at the same time, provided that step 1 is executed previously. to achieve a known power down state in the sensor, execute step 1 before removing any power supplies during the power removal process. figure 31: recommended power down sequence table 16: power down signal timing symbol parameter min typ max unit t 1 standby entry complete 1 frame + 40 C C extclks t 2 active extclk required after standby asserted 10 C C extclks t 3 power supply removal can be in any order and anytime after completion of t 2 0CCextclks ext c lk standby standby asserted t 1 standby mode t 2 t 3 remove power supplies v aa v dd v dd _io
mt9d115 ds rev. e pub. 4/15 en 47 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes standby modes the mt9d115 supports three standby modes: ?soft standby ? low leakage hard standby ? high leakage hard standby for each mode, entry can be overridden by programming the standby_control register. patch codes, pll configurations, parallel an d mipi io selections are retained in all standby modes. soft standby soft standby can be enabled by register access ; it disables the sensor core and most of the digital logic. the two-wire serial interf ace is still active an d the mt9d115 can be programmed through register commands. all register settings and ram content will be preserved. soft standby can be performed in any sequencer state. low leakage hard standby hard standby mode uses the standby signal to shut down digital power (v dd ) and ensure the lowest power consumption. all th e two-wire serial interface settings and firmware variables except patch codes, pll configuration, parallel/mipi io and context selections will be lost in this mode. starting up from this mode is equivalent to power up and current context selections. the two-wire serial interface will be inactive and the sensor must be started up by de-asserting the standby signal. high leakage hard standby (without loss of variable data) high leakage hard standby mode (without the loss of variable data) can also be achieved. this mode stores the variables and state of th e sensor before entering standby (similar to soft standby). the power consumption is lower than that of soft standby, with extclk enabled, as internal clocks are turned off, an d the two-wire serial interface will be inac- tive. because the high leakage hard standby mode (w ithout the loss of variable data) is also activated by standby, the en_vdd_dis_soft register needs to be programmed to indicate the selection of this mode before standby is asserted. de-asserting standby will cause the sensor to come out of the standby mode. this also causes the sensor to resume operation from the state before the standby signal was asserted. by default, asserting the standby signal causes the hard standby mode described above.
mt9d115 ds rev. e pub. 4/15 en 48 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes hard standby mode the mt9d115 can enter hard standby mode by using external standby signal, as shown in figure 32. extclk can be stopped to reduce the power consumption during hard standby mode. two-wire serial interface and ifp block shut down even when extclk is running during hard standby mode. entering standby mode 1. assert standby signal (high). exiting standby mode 1. de-assert standby signal (low). 2. follow ?hard reset? on page 44. figure 32: hard standby mode operation note: in hard standby mode, extclk is automatically gated off, and the two-wire serial interface is not active. table 17: hard standby signal timing symbol parameter min typ max unit t 1 standby entry complete 1 frame + 40 C C extclks t 2 active extclk required after standby asserted 10 C C extclks t 3 active extclk required before standby de-asserted 10 C C extclks t 4 standby time 1 frame + 120 C C extclks t 5 active extclk required before reset_bar asserted 10 C C extclks ext c lk standby standby asserted t 1 standby mode extclk disabled t 2 t 3 extclk enabled t 4
mt9d115 ds rev. e pub. 4/15 en 49 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes soft standby mode the mt9d115 can enter soft standby mode by writing to a sysctl register through the two-wire serial interface, as shown in figu re 33. extclk can be stopped to reduce the power consumption during soft standby mode. however, since two-wire serial interface requires extclk to operate, on semiconductor recommends that extclk run contin- uously. if extclk needs to be stopped, on semiconductor recommends using hard- ware standby mode. entering standby mode 1. sysctl 0x0018[3] must be set to ?1? to ac tivate standby mode. this will generate an interrupt to the mcu when sysctl 0x0018[0] is set to ?1.? 2. set sysctl 0x0018[0] to ?1? to initiate standby mode. 3. check until sysctl 0x0018[14] changes to ?1? to indicate mt9d115 is in standby mode. exiting standby mode 1. reset sysctl 0x0018[0] to ?0.? 2. check until sysctl 0x0018[14] changes to ?0? to indicate the mt9d115 is out of standby mode. figure 33: soft standby mode operation table 18: soft standby signal timing symbol parameter min typ max unit t 1 standby entry complete (r0x18[14] = 1) 1 frame + 40 C extclks t 2 active extclk required after soft standby activates 10 C C extclks t 3 active extclk required before soft standby de- activates 10 C C extclks t 4 minimum standby time 1 frame + 120 C C extclks ex tclk r0x0018[0] mode t 1 t 2 t 4 t 3 poll r0x0018[14] standby mode extclk disabled extclk enabled set r0x0018[0] = 1 s data r0x0018[14] = 1
mt9d115 ds rev. e pub. 4/15 en 50 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor power modes note: x = dont care. table 19: status of signals during different states signal reset post-reset software standby low power hard standby power down d out [7:0] high-z high-z high-z by default (configurable through oe_bar or two-wire serial interface register) high-z by default x pixclk high-z high-z high-z by default (configurable) high-z by default x lv high-z high-z high-z by default (configurable) high-z by default x fv high-z high-z high-z by default (configurable) high-z by default x dout_n 0 0 0 0 x dout_p 0 0 0 0 x clk_n 0 0 0 0 x clk_p 0 0 0 0 x gpio[3:0] high-z high-z depending on how the system uses them as d out _lsb1/d out _lsb0/flash/oe_bar depending on how the system uses them as d out _lsbs/flash/ oe_bar x s addr input input input input s data input i/o input input sclk input input input input
mt9d115 ds rev. e pub. 4/15 en 51 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor other features other features one-time programmable memory (otpm) the mt9d115 contains two bytes of otpm, suitable for storing module identification that can be programmed during the module manufacturing process. programming the otp memory requires the use of a high voltage at the v pp pin. during normal operation, the v pp pin should be left floating. the otpm can be accessed through the two-wire serial interface. programming the otpm refer to tn-09-189: programming otp memory to program the otp memory. sequence of signals for otpm operation reading the otpm reading the otpm data requires the sensor to be fully powered and operational with its clock input applied. the data can be read th rough a register from the two-wire serial interface. reset _bar extclk sclk / s data v pp power supplies information to be programmed to the register initiate programming and poll status bit read programmed values for status
mt9d115 ds rev. e pub. 4/15 en 52 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor other features gpio and output enable controls general purpose i/os the four gpios of the mt9d115 can be configured in multiple ways. each of the i/os can be used as a simple input/output that can be programmed from the host. the status of the gpio is read at power up and can be used as a module id to identify different module suppliers. in addition, module id can be stored in the otp memory of the sensor. information on the otp memory ca n be found in ?one-time programmable memory (otpm)? on page 51. if 10-bit raw output is required, gpio[1:0] can be configured as bit 1 and bit 0 (the lsbs) of a 10-bit data bus. gpio[2] can be configured to output a flash pulse to trigger an external xenon or led flash or a shutter pulse to control an external shutter. gpio[3] can also be configured as an input to be used as an oe_bar signal for the data bus. the general purpose inputs are enabled or disabled through register settings. once enabled, all four inputs must be driven to valid logic levels by external signals. the state of the general purpose inputs can be read from a register. output enable control when the parallel pixel data interface is en abled, its signals can be switched asynchro- nously between being driven and high-z under signal or register control.
mt9d115 ds rev. e pub. 4/15 en 53 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor gpio control gpio control the mt9d115 has four general purpose i/o (gpi o) signals and that can be individually programmed to perform various functions. table 20 describes the gpio registers and variables. overview of gpio signals ? extension of two lower data bits during 10-bit output mode ? external flash control output ? external oe_bar control input for parallel port signals table 20: gpio related registers and variables map address bits descriptions sysctl 0x001a [8] gpio[3] enable. gpio[3] can be configured as an output enable pad. 0: gpio[3] does not function as oe. 1: gpio[3] functions as oe. sysctl 0x001e [6:4] controls the output slew rate of gpio signals. 111 programs the fastest slew rate. refer to ac/dc specification in the data sheet for the numbers. default value is 000 for slowest slew rate. sysctl 0x0024 [3:0] the state of gpio si gnals during power on. read-only. gpio 0x1070 [12:9] gpio data port. state of current gpio signals can be read through this register. gpio 0x1074 [12:9] gpio set command. when gpio is configured as ou tput, setting this register to 1 will write 1 to gpio port. use gpio clear command to clear. gpio 0x1076 [12:9] gpio clear command. when gpio is configured as ou tput, setting this register to 1 will write 0 to gpio port. use gpio set command to set. gpio 0x1078 [12:9] gpio direction control for each gpio signals. 0 = output 1 = input after power-on, gpio ports are in input mode.
mt9d115 ds rev. e pub. 4/15 en 54 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor electrical specifications electrical specifications absolute maximum rating caution table 21 shows stress ratings only, and functi onal operation of the device at these or any other conditions above those indicated in the product specification is not implied. stresses above those listed may cause permanent damage to the device. exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. i/o parameters note: v ih and v il specifications apply to the over- and undershoot (ringing) present in the mclk. table 21: maximum rating symbol parameter rating unit min max v dd _max core digital voltage C0.3 2.4 v v dd _io_max i/o digital voltage C0.3 4.0 v v aa _max analog voltage C0.3 4.0 v vaa_pix_max pixel supply voltage C0.3 4.0 v v dd _pll_max pll supply voltage C0.3 4.0 v v ih _max input high voltage C0.3 v dd _io + 0.3 v v il _max input low voltage C0.3 C v t_op operating temperature (measured at junction) C30 75 c t_st storage temperature C40 85 c table 22: i/o parameters f extclk = 6C54 mhz, v dd = v dd io_tx = v dd _io = 1.8v; v aa = vaa_pix = v dd _pll = 2.8v; t j = 25c symbol parameter min typ max unit note v ih input logic high threshold v dd _io C 0.3 C v dd _io + 0.3 v v il input logic low threshold C 0.1 C 0.6 v v dd _io = 2.8v C 0.1 C 0.3 v v dd _io = 1.8v v oh output logic high threshold v dd _io C 0.3 C C v at specified at i oh v ol output logic low threshold C C 0.3 v C c in input pins - (sclk, s data ) capacitance C3.53.9pfC c load output pins - (s data ) load capacitance CC30pfC p up _s data s data pull-up resistor C 1.5 C k ? C
mt9d115 ds rev. e pub. 4/15 en 55 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor electrical specifications mipi interface ac and dc electrical specifications introduction the mipi interface for the mt9d115 image sens or was designed to meet the mipi alli- ance specification for d-phy version 1.0. pl ease refer to this document for details on the mipi specification and usage. electrical specifications . table 23: mipi high-speed transmitter dc characteristics f extclk = 48 mhz; v dd = v dd _tx = v dd _io = 1.8v; v aa = v aa _pix = v dd _pll = 2.8v; ambient temperature parameter description min nom max units v cmtx hs transmit static comm on mode voltage 150 200 250 mv | ? v cmtx (1,0)| v cmtx mismatch when output is differential-1 or differential-0 16 mv |v od | hs transmit differential voltage 140 200 270 mv | ? v od |v od mismatch when output is differential-1 or differential-0 14 mv v ohhs hs output high voltage 360 mv z os single-ended output impedance 39 50 64 ohm ? z os single-ended output impedance mismatch 10 % table 24: mipi high-speed transmitter ac characteristics f extclk = 48 mhz; v dd = v dd _tx = v dd _io = 1.8v; v aa = v aa _pix = v dd _pll = 2.8v; ambient temperature parameter description min nom max units t r and t f 20%-80% rise time and fall time 150 ps table 25: mipi low-power tran smitter dc characteristics f extclk = 48 mhz; v dd = v dd _tx = v dd _io = 1.8v; v aa = v aa _pix = v dd _pll = 2.8v; ambient temperature parameter description min nom max units v oh thevenin output high level 1.1 1.2 1.4 v v ol thevenin output low level -50 50 mv z olp output impedance of lp transmitter 110 ohm table 26: mipi low-power transmitter ac characteristics f extclk = 48 mhz; v dd = v dd _tx = v dd _io = 1.8v; v aa = v aa _pix = v dd _pll = 2.8v; ambient temperature parameter description min nom max units trlp/tflp 15%-85% rise time and fall time 25 ns treot 30%-85% rise time and fall time 35 ns ? v/ ? tsr slew rate @ c load = 70pf 83 122 mv/ns c load load capacitance 0 70 pf
mt9d115 ds rev. e pub. 4/15 en 56 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor electrical specifications ac electricals figure 34: output interface timing waveforms table 27: ac electricals f extclk = 6C54 mhz, v dd = v dd io_tx = v dd _io = 1.8v; v aa = vaa_pix = v dd _pll = 2.8v; t j = 25 symbol parameter conditions min typ max unit note fextclk external input clock frequency 6 - 54 mhz 2 tr external input clock rise time from10% to 90% of vp-p - 2 5 ns 1 tf external input clock fall time from10% to 90% of vp-p - 2 5 ns 1 dcextclk external input clock duty cycle 40 50 60 % tjitter external input clock jitter peak-to-peak - - 500 ps tcp extclk to pixclk propagation delay 5- 45ns3 fpixclk pixel clock frequency 6 - 85 mhz trpixclk pixel clock rise time cload = 15pf - 2 5 ns tfpixclk pixel clock fall time cload = 15pf - 2 5 ns tpd pixel clock to data valid - - 0.6*pixclk ns 4 tpfh pixel clock to frame valid high - - 0.6*pixclk ns tplh pixel clock to frame valid low - - 0.6*pixclk ns tpfl pixel clock to line valid high - - 0.6*pixclk ns tpll pixel clock to line valid low - - 0.6*pixclk ns pixclk pin slew rate programmable slew = 7 v dd _io = 2.8v, cload = 45pf - 1.2 - v/ns 5 v dd _io = 1.8v, cload = 45pf - 0.6 - v/ns programmable slew = 4 v dd _io = 2.8v, cload = 45pf - 1 - v/ns v dd _io = 1.8v, cload = 45pf - 0.5 - v/ns programmable slew = 0 v dd _io = 2.8v, cload = 45pf - 0.3 - v/ns v dd _io = 1.8v, cload = 45pf - 0.15 - v/ns
mt9d115 ds rev. e pub. 4/15 en 57 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor electrical specifications notes: 1. measured when the pll is off. specification not applicable when pll is on, but input high/low voltage should be within specification. 2. vih and vil specifications apply to the over - and undershoot (ringing) present in the mclk. 3. measurement done with pll off. 4. valid for cload<20pf on pixclk, d out [9:0], line_valid, and frame_valid pads. loads must be matched as closely as possible. 5. pll is off and extclk is 24mhz. output pin slew rate programmable slew = 7 v dd _io = 2.8v, cload = 45pf - 1.6 - v/ns 5 v dd _io = 1.8v, cload = 45pf - 0.8 - v/ns programmable slew = 4 v dd _io = 2.8v, cload = 45pf - 1.25 - v/ns v dd _io = 1.8v, cload = 45pf - 0.55 - v/ns programmable slew = 0 v dd _io = 2.8v, cload = 45pf - 0.3 - v/ns v dd _io = 1.8v, cload = 45pf - 0.15 - v/ns table 28: dc electricals setup conditions: f extclk = 6-54mhz, v dd = v dd _io_tx = v dd _io = 1.8v; v aa = vaa_pix = v dd _pll = 2.8v; t j = 25 c, unless stated otherwise symbol parameter condition min typ max unit note s v dd digital core supply voltage 1.7 1.8 1.95 v v dd _pll pll supply voltage 2.5 2.8 3.1 v vaa analog supply voltage 2.5 2.8 3.1 v vaa_pix pixel supply voltage 2.5 2.8 3.1 v v dd _io digital io supply voltage for v dd _io = 1.8v 1.7 1.8 1.95 v for v dd _io = 2.8v 2.5 2.8 3.1 v v dd io_tx mipi supply voltage 1.7 1.8 1.95 v vpp otpm supply voltage - 8 - v idd_io digital io supply current context a v dd _io =1.8v - 10 - ma 1 v dd _io = 2.8v - 15 - ma context b v dd _io = 1.8v - 12 - ma v dd _io = 2.8v - 20 - ma idd_pll pll supply current pll is off - n/a - ma pll is on - 13 18 ma 2 idd digital core supply current operating in parallel mode context a - 15 30 ma iaa analog supply current - 40 50 ma iaa_pix pixel supply current - 1.5 3 ma iddio_tx mipi supply current - n/a - ma 3 idd digital core supply current context b - 25 52 ma iaa analog supply current - 40 52 ma iaa_pix pixel supply current - 0.8 3 ma iddio_tx mipi supply current - n/a - ma 3 table 27: ac electricals f extclk = 6C54 mhz, v dd = v dd io_tx = v dd _io = 1.8v; v aa = vaa_pix = v dd _pll = 2.8v; t j = 25 symbol parameter conditions min typ max unit note
mt9d115 ds rev. e pub. 4/15 en 58 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor electrical specifications notes: 1. v dd _io current is dependent on the output data rate. 2. pll is on with 85 mhz output frequency setting. 3. v dd _io_tx current is only applicab le in serial output mode. 4. pll is on with 480 mhz vco frequency settings. 5. either with extclk running or extclk stopped an d exclk pin is either pulled up or pulled down. measured at t j = 70 c. 6. extclk is stopped and exclk pin is either pulled up or pulled down. 7. extclk running at 27 mhz. i dd digital core supply current operating in serial mode context a - 23 50 ma 4 i aa analog supply current - 40 50 ma i aa _pix pixel supply current - 1.5 3 ma i dd io_tx mipi supply current - 5 3 ma i dd digital core supply current context b - 35 70 ma i aa analog supply current - 40 70 ma i aa _pix pixel supply current - 0.8 3 ma i dd io_tx mipi supply current - 8 10 ma i hardstandby total standby current standby pin asserted, r0x0028=1 - - 20 ? a5 i hardstandby standby pin asserted, r0x0028=0 - - 90 ? a7 i softstandby r0x0018[0]=1 - - 90 ? a6 i softstandby r0x0018[0]=1, r0x0028=0 - - 2 ma 7 i softstandby r0x0018[0]=1, r0x0028=1 - - 3 ma 7 table 28: dc electricals (continued) setup conditions: f extclk = 6-54mhz, v dd = v dd _io_tx = v dd _io = 1.8v; v aa = vaa_pix = v dd _pll = 2.8v; t j = 25 c, unless stated otherwise symbol parameter condition min typ max unit note s
mt9d115 ds rev. e pub. 4/15 en 59 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition appendix a- v dd _io current addition introduction this appendix describes the system requirem ents to achieve lowest power consumption in the v dd _io domain during low power hardware standby mode in on semicon- ductor's mt9d115 cmos digital image sensor. v dd _io current v dd _io current is used to measure the power consumption of the io pad ring of our sensor. therefore, it is extremely system-dependent and greatly affected by the external conditions as current can flow out of the chip through the io ring and into the system. in this document, we outline requirements at the system level to achieve minimum power consumption during low power hardware standby mode. to achieve the lowest v dd _io current, it is critical to match v dd _io level in the sensor and the controller. otherwise, there can be elevated current drawn on the v dd _io due to mismatch in termination voltage level on th e sensor pins. in on semiconductor system design, the io voltage between the sensor and the controller is matched by using the same voltage regulator, as shown in figure 35. this is recommended for both the system design and setup to measure the v dd _io power consumption. figure 35: recommended system and test setup for minimum v dd _io power consumption s clk s data controller m t9d113 reset_ bar, standby s addr , extclk pixclk, frame_valid, line_valid, d out [7:0], g p io[1:0] drive high h igh-z h igh-z drive low input vio_controller v dd _io gnd gnd 2. 2k voltage regulator vreg gnd gpio[3:2]
mt9d115 ds rev. e pub. 4/15 en 60 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition io pin states in addition to matching v dd _io levels between the controller chip and the sensor, the control signals to the input pins of the sens or must be at a specified level to achieve minimal v dd _io current draw. table 29 shows the pin states recommended to achieve minimum v dd _io current during hardware standby mode. it is always a good practice to measure th e pin voltage during hard standby and try to match the recommended pin state. notes: 1. v il specification for input signal applies. refer to table 20, gpio related registers and variables, on page 53. 2. v ih specification for input signal applies. refer to table 20, gpio related registers and variables, on page 53. 3. these pins are not directly connected to v dd _io supply but through a voltage follower to the con- troller. 4. the pins on the controller connected to these sensor pins are input pins. 5. these pins are not directly connected to v dd _io supply but through the controller. 6. these pins are not directly connected to gnd but through the control signal on the controller. 7. these pins are floating in parallel mode operation. 8. tie all the unused gpio pins to d gnd or v dd _io level in the module. 9. if gpio3 is connected to gpio pin on the controller, program gpio3 as an input before low power hard standby mode and drive gpio3 externally from the controller to d gnd level. table 29: status of sign als during standby state signal state on sensor pin on semiconductor test system note d out [7:0] high-z by default (configurable through oe_bar or two- wire serial interface register) no control 4 pixclk high-z by default (configurable) line_valid high-z by default (configurable) frame_valid high-z by default (configurable) gpio[3:0] depending on how the system uses them as d out _lsb1/d out _lsb0/flash/oe_bar pulled to gnd 8, 9 d out _n 0 float 7 d out _p 0 clk_n 0 clk_p 0 s addr input pulled to gnd 1, 6 extclk input s data input high z 3 sclk input reset_bar input pulled to v dd _io level 2, 5 standby input
mt9d115 ds rev. e pub. 4/15 en 61 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition reset_bar with internal pull-up the reset_bar pin has an internal pull-up device to v dd _io (see figure 36). figure 36: reset_bar pad architecture since r pullup is active devices connected in triode state, the value of r pullup is depen- dent on the difference between v dd _io and vpad level (see table 30). note: the above data is for engineering purposes only. these represent typical values that can be expected. table 30: typical mismatch current in v dd _io due to mismatch in reset_bar level and v dd _io level conditions: v dd = v dd _io_tx = 1.8v; v aa = v aa _pix=v dd _pll=2.8v; tj=30 c, extclk is off and tied to gnd level. all other pin states and levels are set accordin g to on semiconductor e2e on pin states. v dd _io vpad min typ max unit 1.80 1.70 14 18 22 ? a 1.80 2 5 10 1.95 C13 C17 C21 2.80 2.50 61 67 72 2.80 2 7 12 3.10 C54 C60 C66
mt9d115 ds rev. e pub. 4/15 en 62 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition recommended system and test setup with multiple serial interface slave devices the recommended system and test setup show n in figure 37 is only valid for a system where mt9d115 is the only two-wire serial interface slave device connected to the controller chip. as the s clk and s data are to be pulled high to the v dd _io level during the hardware standby to minimize the io current consumption due to the data toggling in the two-wire serial interface, this design is not feasible if there is an additional slave device sharing the same two-wire serial interface on the controller chip. in such systems, it is recommended to have a voltage follower to isolate the pull-up resistors attached between the two-wire serial interface and v dd _io supply of mt9d115 as shown in figure 37. otherwise, the data toggling from the two-wire serial interface transactions to other could cause leakage from the v dd _io supply of mt9d115. figure 37: recommended system and test setup for minimum v dd _io power consumption in the mt9d115 sharing with multiple two-wire serial interface devices in addition, in some system designs where the io level of the additional devices sharing the same two-wire serial interface with mt9d115 is different from that of mt9d115, it is recommended that the io voltage level between the controller and the mt9d115 be maintained to the same level by sourcing from the same voltage regular as shown in figure 38 on page 63. sclk s data c ontroller mt9d113 r eset_bar, standby s addr ,extclk pixclk, frame_valid,line_valid, d out [7:0], g p io [1:0] drive high x x drive low input vio_controller v dd _io gnd gnd voltage r egulator vreg gnd other slave devices voltage follower gpio[3:2]
mt9d115 ds rev. e pub. 4/15 en 63 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition figure 38: recommended system and test setup for minimum v dd _io power consumption in the mt9d115 sharing with multiple two-wire serial interface devices at different io levels for a system which uses separate voltage regulators for mt9d115 sensor and the controller chip as shown in figure 39, it is important to match the voltage levels between two regulators as close as possible. if the voltage levels are not matched, there can be additional current consumption in the v dd _io domain connected to the sensor. this additional current is generated in the intern al pull up resistor present in reset_bar pad and external resistors used for two-wire serial interface. the current leakage from the voltage level mismatch in reset_bar pad can be charac- terized as follows: i dd _iomismatch = (vreg2 - vreg1)/ rpullupreset_bar@v dd _io the internal pull up resistance is dependent on the v dd _io level. typical levels of mismatch current at different v dd _io levels can be found in table 30 on page 61. sclk s data c ontroller mt9d113 r eset_bar, standby s addr ,extclk pixclk, frame_valid,line_valid, d out [7:0], g p io [1:0] drive high x x drive low input vio_controller v dd _io gnd gnd voltage r egulator vreg1 gnd other slave devices voltage f ollow er voltage r egulator vreg2 gpio[3:2]
mt9d115 ds rev. e pub. 4/15 en 64 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition figure 39: system setup with independent voltage sources for mt9d115 and controller chip s clk s data c ontroller dut r eset_bar, standby s addr ,extclk pixclk, frame_valid, lin e_valid d out [7:0], g p io[1:0] drive high high-z high-z drive low input vio_controller v dd _io 2.2k voltage r egulator vreg1 voltage regulator vreg2 gpio[3:2] gnd gnd gnd gnd
mt9d115 ds rev. e pub. 4/15 en 65 ?semiconductor components industries, llc,2015. mt9d115: 1/5-inch soc digital image sensor appendix a- v dd _io current addition test sequence for measuring v dd _io current at hard standby mode follow the procedure defined within the sensor data sheet. the following test sequence takes the mt9d115 as a reference. contact your local on semiconductor applications engineer for any specific product. to m e asure v dd _io current at hard standby mode: 1. supply pwrdn (also known as standby) pin (j11 pin2) with 0 volt externally. 2. supply the reset_bar pin (u22 pin4) with v dd _io volt externally. 3. connect an ammeter between i dd _io (j9) and d gnd . 4. use jumpers j5, j17, and j20 to make sure gpio pins are connected to either gnd or v dd _io. at this point, the part is in operating mode an d it is possible to load an .ini file to get an image with devware. 5. supply the pwrdn pin with v dd _io volt externally and wait for one frame + 50 clock. at this stage, the part is in hard standby. 6. by removing j1, the extclk is disconnect ed to the part and then connect extclk pin (j1 pin2) to either d gnd or v dd _io. 7. now the part is in hard standby with extclk off. the user can read off the v dd _io current from the amme ter at step 3 above. figure 40: modifications to the demo2 sensor head board for v dd _io current measurement | ? 2009 aptina imaging corporation | aptina confidential 2 modifications ?2008 micron j9 jumper removed to monitor iddio by connecting ammeter on pins 1 and 2 to control the reset pin externally, u22 was removed and a 10kohm resistor connected to pin 4, which is connected to a 2.8v external source j11 jumper removed to control the standby or pwdn pin externally. a 10k resistor is connected for pull- up on this pin. in 2 in operating= 0v, hard standby= 2.8v using external voltage source. j1 jumper for clock conclusion it is important from the system perspectiv e to ensure io levels between mt9d115 and the controller chip at the same potential level to achieve minimum io power consump- tion in mt9d115. a system configuration to ac hieve this is proposed in this document. in addition, suggestion s on how to approach system designs with multiple two-wire serial interface devices and multiple io level devices are provided.
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